The present invention relates to the field of programmable oscillators, and more particularly to systems and methods including high accuracy EPROM programmable phase locked loop oscillators.
The CY2037 from Cypress Semiconductor Corporation (San Jose, Calif.), is an EPROM-programmable (electrically programmable read only memory), high-accuracy and resolution, PLL-based (phase-locked loop) digitally controlled crystal oscillator (DCXO). The device has a low jitter specification, e.g.,  less than xc2x1100 ps (pkxe2x80x94pk) at 5V and f greater than 33 MHz and  less than xc2x1125 ps (pkxe2x80x94pk) at 3.3V and f greater than 33 MHz. The device is available die form, i.e., without packaging, and attaches directly to a 10-30 MHz crystal. The oscillator device may be packaged into various through-hole or surface mount packages. A block diagram of this circuit is shown in FIG. 1A.
Traditionally, an oscillator crystal is calibrated in an operation termed the xe2x80x9cfinal platexe2x80x9d, from an initial accuracy of within 2,000-3,000 ppm from the nominal frequency desired to within 10-25 ppm (typical) from the nominal desired frequency. This is a significant mechanical step, and constitutes the final calibration of the oscillator after it is mounted in a module. The final plate involves selectively depositing a film or plating of metal on a prepared pre-plate portion of the surface of the crystal, to mechanically alter the resonant frequency of the crystal. This process is typically manually assisted, requiring a skilled technician to carefully apply the plating to adjust the operating frequency of the crystal. Not only the thickness, but also the placement of the plating is critical; if it is not exactly concentric over the pre-plate region, phase noise and jitter are increased. In fact, as a rule, phase noise and jitter increase after the final plate. The final plate process also results in loss of yield. For example, there is a probability of plating adhesion failure. Further, the final plate process is performed with the crystal exposed, and thus more sensitive to environmental influences. After the crystal is tuned by the final plate, the crystal is sealed. Thus, the final plate process is expensive, labor consuming, reduces crystal quality, and potentially induces defects.
Precision crystal oscillators (PXO) such as the Micro Analog Systems (Espoo, Finland) MAS9271 and MAS1173, which include a digitally controlled capacitive tuning network for trimming a crystal frequency, are typically calibrated and operated independently of a digital frequency synthesizer. Thus, using a PXO, a crystal is tuned to a desired frequency, to within a small tolerance. This may include a final plate process. The digital frequency synthesizer is then programmed using the nominal multiply and divide values to achieve the desired output frequency.
In principle, the oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping from an oscillator manufacturer. This would enable fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals or inventory of customized assemblies. In this case, the oscillators are not field programmable, and an integrator of oscillators into products must still specifically order a particular oscillator at a predefined frequency, and must still await the customization by the oscillator manufacturer and incur potential set-up charges, which may be significant for small orders, as well as the added cycle time of days or weeks.
The CY2037 contains an on-chip oscillator and a separate oscillator tuning circuit for fine-tuning of the output frequency. The crystal capacitive load can be selectively adjusted by programming a set of seven EPROM bits. This feature is typically used to compensate for crystal variations or to obtain a more accurate synthesized frequency.
The typical use of a programmable oscillator starts with an oscillator crystal trimmed to a nominal value. Then, the oscillator circuit is permanently programmed (in EPROM) with the multiply and divide ratios. Finally, at least in the case of the CY2037, the operating frequency of the crystal is tuned with the tuning bits to achieve a desired maximum error.
The CY2037 PLL die has a very high resolution. It has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with low error, for example zero or low parts per million (ppm) The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can be selected as either the PLL or crystal oscillator output, providing a total of sixteen separate output options. The output is selectable between TTL and CMOS duty cycle levels.
The nominal output frequency of the PLL is determined by the following formula:
FPLL=2xc3x97(P+5)/(Q+2)xc3x97FREF
where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values.
One version of the CY2037 contains a special tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven logarithmically sized load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM programmable with seven Osc_Tune bits, and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17 pF to 8 pF for an approximate 100:1 total control ratio.
The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs can be generated up to 250 MHz. According to the design, the entire configuration of the EPROM can be reprogrammed one time, allowing programmed inventory to be altered or reused. The CY2037 includes a 44 bit by 2 row EPROM block, which holds all of the configuration information. The programming word contains the data from the EPROM and a row select (RowSel) bit, which determines the row being accessed during normal operation. Cypress advises that the bit should match in both rows, and therefore, when row 0 is programmed, row 1 is otherwise left unprogrammed, with the RowSel bit row 0 programmed to 0. When row 1 is programmed, the RowSel bit of row 0 is programmed to 1, a permissible overwrite.
The CY2037 contains a shadow register in addition to the EPROM register, which is optionally disabled. The shadow register is an exact copy of the EPROM register and is the default register when the Valid bit is not set. It is useful when the prototype or production environment calls for measuring and adjusting the CLKOUT frequency multiple times. Multiple adjustments can be performed with the shadow register. Once the desired frequency is achieved, the EPROM register is permanently programmed.
Accordingly, the following essential features of the CY2037 are controlled based on data stored in the EPROM; Feedback counter value (P); Reference counter value (Q); Output divider selection; Oscillator Tuning (load capacitance values); Duty cycle levels (TTL or CMOS); Power management mode (OE or PWR_DWN); Power management timing (synchronous or asynchronous); and Output Source Frequency (PLL or Crystal).
A PLL-based frequency synthesizer uses a reference input to generate output clocks. The reference can be provided by a quartz crystal or an external clock source. The accuracy and stability of the output clocks in a PLL-based frequency synthesizer are directly proportional to those of the reference. Thus, it is important to provide a stable, accurate, and appropriate reference input.
Jitter is an effect caused by an irregularity in the crystal oscillation and/or logic transitions of the circuit electronics. This can be caused by rapid changes in power supply voltage, logic transition voltage, stochastic processes, radio frequency interferences, or the like.
FIG. 1 shows the block diagram of a CY2037 PLL-based frequency synthesizer. The reference input to the PLL comes from an on-chip crystal oscillator. FIG. 2 shows the circuitry of the on-chip crystal oscillator (a.k.a. Pierce oscillator), which is formed by components R. G, Ci and Co, where G is a linear inverter. For this circuit to produce an electrical clock, a quartz crystal needs to be connected between the XTALIN and XTALOUT pins.
The equivalent circuit of a Quartz crystal is shown in FIG. 3. C0 is the shunt or static capacitance of the crystal. R1 is the motional resistance, L1 is the motional inductance, and C1 is the motional capacitance of the crystal. R1, L1 and C1 are determined by the mechanical properties of the crystal (they are in the motional arm of the crystal and their circuit effects only exist when the crystal is oscillating). The effective reactance curve of the crystal is shown in FIG. 4. Thus, it is seen that slight variations in the fabrication of the quartz crystal will alter the nominal output frequency.
When connected as a feedback element in a oscillator circuit that has a 0xc2x0 phase shift, the crystal oscillates at the series resonating frequency (f s) given by Eq. 1:
fs=1/(2xcfx80(L1C1))xe2x80x83xe2x80x83Eq. 1
A Pierce oscillator has a 180xc2x0 phase shift on the amplifier and needs another 180xc2x0 phase shift from the feedback element. The feedback element in this case is a crystal along with a capacitive load, and the frequency of oscillation of the crystal (and oscillator circuit) is in the xe2x80x9carea of parallel resonancexe2x80x9d. The actual value of the crystal oscillator parallel resonating frequency is dependent on the capacitive loading seen by the crystal and is given by Eq. 2:
fp=fs(1+C1/2(C0+CL)xe2x80x83xe2x80x83Eq. 2
where CL=Capacitive loading seen by the crystal.
For example, a parallel resonant crystal tuned to a particular Cload, will oscillate at a predetermined frequency when it is placed in a Pierce oscillator (parallel oscillator) circuit which offers a capacitive loading CL=Cload. If the capacitive loading seen by the crystal in the Pierce oscillator circuit were different from the rated Cload, the change in frequency from the rated frequency is given by Eq. 3:
(fp(rated)xe2x88x92fp(actual))/fp(rated)=C1/2((1/(C0+CL)xe2x88x921/(C0+CL))xe2x80x83xe2x80x83Eq. 3
where:
fp(rated)=frequency rating of crystal
fp(actual)=actual frequency of oscillation in oscillator circuit
Cload=Capacitive loading rating of crystal
CL=Capacitive loading seen by crystal in oscillator circuit.
Thus, a trim capacitor network would be expected to tune the circuit for variations in the crystal, allowing fine calibration of the operating frequency. This effect is analytic, and therefore the alteration in operating frequency due to a change in capacitance may be predicted with accuracy.
Typically, the selected EPROM register of the CY2037 device is programmed with appropriate multiply (P) and divide (Q) ratios, to achieve a desired output frequency, typically slightly above the desired final frequency. The controller calculates the multiply and divide ratios based on the output of the frequency counter and an algorithm therein, known in the art. After the P and Q are programmed into the device, the output of the oscillator is measured over a number of conditions of tuning, for example testing the effect on the output for each of the tuning bits. The controller then determines an optimal set of tuning bits and these are programmed into the EPROM. Thus, the DCXO is normally first programmed based on a nominal oscillator frequency, and the oscillator frequency then adjusted by trimming to achieve the desired output.
Oscillators will often have an intrinsic sensitivity to temperature. Thus, the output frequency will vary from a nominal value with changes in operating temperature. It is known to compensate for these changes using a so-called TCXO, or temperature compensated crystal oscillator. The temperature compensation network may be analog or digital. Often, it is desired to provide a crystal controlled oscillator with a stable frequency, which is controllable by an external voltage. This is called a voltage controlled crystal oscillator, or VCXO. For example, high precision phase locked loops, and radio frequency transceivers may use these devices. Many TCXO devices also provide VCXO functionality, and are called voltage controlled, temperature compensated crystal oscillators (VCTCXO).
Essentially, modem TCXO and VCXO devices operate by altering a capacitive loading on the oscillator crystal in dependence on a sensed voltage. This is typically performed using a varactor (a diode whose capacitance varies with reverse-bias voltage), which responds to an analog control voltage. This provides a stepless analog control, in contrast to the use of switched capacitor networks used to trim the capacitive load.
Micro Analog Systems (Espoo, Finland, www.mas-oy.com) produces a voltage controlled, temperature compensated crystal oscillator (VCTCXO) circuit, MAS1175, a block diagram of which is shown in FIG. 8, which provides a three point temperature compensation, a serial bus for programming and trim, EPROM storage of parameters, and analog compensation. Thus, a digital capacitive trimming network and analog capacitive control network are both provided. The circuit requires an external crystal and varactor.
The present invention provides a number of enhancements to digitally controlled oscillator systems. According to a first embodiment, the present invention provides a system and method for field programming an EPROM programmable oscillator device, using a relatively simple programmer device and a terminal or personal computer.
According to another aspect of the invention, the final plate process for tuning the crystal is eliminated, and the processes of electronically tuning the crystal and selecting operating parameters for a digital frequency synthesizer are consolidated in a single process. Thus, by treating the tuning registers for the crystal oscillator as an integral part of the frequency control of the output, a production step is eliminated, greater flexibility in selecting operating parameters is obtained, and quality is improved.
The EPROM programmable oscillator device preferably includes electronically controllable tuning of crystal frequency as well as high precision frequency synthesis. According to the present invention, these two attributes are combined to dispense with the necessity of the final plate, and, for example, to thereby increase output quality (reduced phase noise and jitter), increase product quality (reduce probability of environmental contamination of crystal or delamination of plating), decrease costs, decrease skilled manual labor required, decrease manufacturing cycle time (and allow decentralization of final production steps with field programmability), allow standardization of completely manufactured oscillators, and/or increase manufacturing yield.
The present invention also provides a further enhancement for reducing oscillator jitter. In testing an oscillator designed using a quartz crystal and CY2037 packaged in an industry standard 5xc3x977 mm metal package with ceramic substrate, over a frequency range (output) of 10-120 MHz, jitter ranged from 95-220 ps (bimodal distribution)(25,000 samples). However, when an internal power supply bypass capacitor of between 10 nF and 100 nF was placed inside the package, jitter was reduced to between 55-120 ps (Gaussian-type distribution) (25,000 samples). Typically, bypass capacitors are placed on the component circuit board, not within the oscillator package, therefore, this significant advantage was surprising. It is likely that this reduction in jitter results from the inductance of the package leads. By providing the bypass capacitor within the oscillator package, the circuit is better isolated from the effects of this inductance. According to the present invention, it is also possible to provide the internal bypass capacitor in conjunction with tuning the inductance of the power supply lines leading to the circuit, to form a filter, to further reduce jitter.
Advantages of field programmability include reduced prototype and manufacturing cycle time, and allowing oscillator users to inventory unprogrammed parts, which are programmed to specification as needed.
Oscillators according to the present invention provide programming capability of greater than 6 significant digits of accuracy, over a frequency range of 1 to 250 MHz, covering both the commercial and industrial temperature ranges. Temperature compensated versions as well as voltage controlled versions, are also within the scope of the invention.
In order to provide a temperature-compensated high-resolution digitally controlled oscillator, one embodiment provides a VCTCXO circuit output as an input (replacing the crystal at XG) for the CY2037 DCXO. The internal trim capacitors of the CY2037 are not employed, and versions of the device where these are unavailable may be employed. In programming this system, the VCTCXO control parameters are first calculated, for example with compensation determined at three different temperatures. The control parameters may be programmed, to test the nominal (untrimmed) output, or the predicted output may be used, but the trimming network parameters remain unprogrammed. The various P, Q and divider values of the DCXO and the capacitive trimming network parameters may together be calculated and then programmed.
Likewise, the present invention also provides an integrated (e.g., single integrated circuit) high resolution DCVCTCXO. In this case, the internal capacitive trimming may coexist with the temperature compensation, voltage control and logic control circuitry. Advantageously, the control electronics for all functions use a single serial interface and set of non-volatile control registers.
The process for programming the DCXO (CY2037) essentially determines the free crystal oscillator operating frequency, for example over a range of available tuning values, and then calculates the optimal P, Q, divider select and tuning value to achieve the desired oscillator operating frequency with acceptable error (ppm), with the lowest Q value. Therefore, in contrast to typical prior art methods, the crystal tuning is performed simultaneously with selection of oscillator parameters P, Q, and divider select, rather than beforehand. This results in greater flexibility for optimizing the various parameters. In this process, therefore, the P, Q and divider select parameters may vary between oscillators that meet the same output frequency specification, due to differences in the crystal and tuning parameters.
Therefore, one aspect of the invention provides a high precision oscillator system that does not require a finely tuned oscillator crystal. Another aspect of the invention provides that the oscillator is programmed with both fine-tuning of crystal operating frequency and output frequency translation in a consolidated operation. A further aspect of the invention provides a programming device for a programmable oscillator, which selects optimum crystal frequency tuning and frequency synthesis in a single operation.
Therefore, the present invention provides a human user interface system and method that provides an interface with a programmable oscillator device, for programming thereof, which meet all or some of the objects identified herein.
Initially, the nominal frequency of the crystal is measured using a frequency counter. This frequency is preferably measured with the programmable oscillator in an unprogrammed state, such that the crystal frequency itself is measured. Preferably, the tuning sensitivity of the system is also measured, by testing the crystal output over a range of available tuning values. Typically, a small number of measured values are required, for example, eight measurements within a seven-bit tuning system. While the output frequency for each bit combination could also be measured, e.g., all 128 values for a seven bit range, but this is not necessary, as the tuning effects may generally be accurately predicted based on a sparse sampling of this range, preferably testing the sensitivity of each bit, but not necessarily separately. The tuning effects of bits, which represent added capacitance on the crystal, and which lower its operating frequency, are typically non-linear; therefore, a lower order bit will have a reduced effect on output, e.g., result in a lower ppm change, when the total capacitance load on the crystal is higher.
The sensitivity of the tuning bits is tested using a temporary programming technique. e.g., a shadow register. By altering the contents of the shadow register, the capacitive effect of the tuning capacitor loading on the crystal is determined without permanently modifying the oscillator. Thus, the tuning sensitivity may be determined before programming the oscillator, which in the unprogrammed state (e.g., CY2037) outputs the crystal reference without regard for the P, Q and divider select.
In the case of a DCVCTCXO, (e.g., combination MAS1175 and CY2037), the temperature compensation network (e.g., MAS1175) may also be maintained in an unprogrammed state until the coefficients for the digital PLL divider network (CY2037) are calculated. This allows, in the event of an undersirable set of P, Q, and divider ratio, a selection of an alternate set of temperature compensation parameters (than those provided by the normal algorithm) to be programmed. Thus, in the same way that the trim capacitor values are temporarily calculated in a DCXO embodiment before storage in non-volatile memory, likewise, the temperature compensation circuit may also be used to provide an additional variable to optimize the circuit performance.
After the base frequency and tuning sensitivity of the oscillator are determined, an optimum set of tuning bits, multiply and divide (P and Q) ratios and divider select is determined to minimize ppm error. Since the tuning bits are uncommitted before programming, this provides an additional degree of freedom for selection of the programming conditions of the oscillator as compared with prior designs. In conjunction with high precision P and Q parameters, the method and system according to the present invention achieves higher quality, lower costs, and field programmability. Advantageously, the crystals do not undergo a final plate process, and thus retain low phase noise and jitter.
After the tuning sensitivity is determined, multiply, divide and divider select parameters are calculated, and all are programmed into the device, i.e., in non-volatile memory. Advantageously, a CY2037 device permits a second programming of the oscillator time, in a second register set, allowing device reuse or reallocation, and further minimizing scrap.
The frequency of the oscillator is determined with a frequency counter, which may be internal to the programming device or provided as an external system. Preferably, the system architecture provides a personal computer for interface and control, a frequency counter, for example an IEEE-488 device, and a personality module that performs the direct logical interfacing with the oscillator. However, a single system may be provided, or the functions separated between modules differently. The personality module may be a low cost design, allowing separate dedicated personality modules to be provided for each particular type of oscillator device. The personal computer and frequency counter may be general resources, and need not be dedicated to oscillator programming. It is noted that the personal computer is merely a convenient interface and processing resource, and may be substituted as desired. Using a modern generation personal computer, the entire programming operation is completed in less than 20 seconds per oscillator.
Another embodiment of the invention integrates all required interface and intelligence within the personality module, which in this case is a complete programmer. Likewise, the personality module may include an embedded Web server and communicate with an arbitrary device through a TCP/IP protocol, over any conveniently provided physical transport layer. Because the set of parameters to be analyzed for optimality is large, and the personality module, without having to search the parameter space for the optimum solution, requires little intelligence, it is preferred to employ a separate processor for determining the optimal parameters.
It is also possible to leave the tuning bits unprogrammed, operating the oscillator through the contents of the shadow register. This allows, for example, digital control over the tuning during operation, for example to construct a digital temperature compensated oscillator (TCXO). On the other hand, traditional TCXO compensation techniques may also be employed, with the device including analog temperature compensation network (such as the MAS1175) subjected to the tuning and parameter optimization process. In the case of a digital TCXO, a simple thermal sensor interfaces with a simple microcontroller, which then reprograms the tuning bits in the shadow register as necessary to maintain the desired output frequency. Such a digital scheme may also be employed to generate a spread spectrum oscillator output, a fine chirp, or other desired waveforms.
The typical programming algorithm according to the present invention is executed based on the following scheme. An error tolerance is defined, which is the ppm error from a nominal output frequency. The crystal frequency and tuning sensitivity is determined. The algorithm then searches for sets of parameters that translate the measured crystal frequency into the desired frequency, within the error tolerance band. It is generally desirable to employ the lowest divide ratio, Q. The divider select factor provides octave scaling of the frequency over a range of, e.g. seven octaves (CY2037). Therefore, the algorithm searches the parameter space in order of ascending Q for acceptable parameter sets.
In order to achieve low ppm error, phase noise and jitter, it is often desirable to prioritize available parameter sets by Q, ppm error, and divider select, at a mid-tuning range nominal tuning value. The parameter sets are also searched for acceptable sets using tuning values other than the nominal. If necessary, the effect of a proposed tuning value may be tested, to ensure that the results are as expected.
As stated above, where an external temperature compensation network is provided, the tuning function is generally incorporated in this external compensation network. However, the preferred programming method is similar, and involves deferring committing to oscillator trimming values until after the DCXO parameters are selected.
A typical acceptable DCXO error tolerance is 150 ppm, which may be available without use of tuning values at all. On the other hand, according to the present invention, the error may typically be held to within xc2x11 ppm. In this case, it is often desirable to activate the four high tuning bits, since this will increase the tuning resolution of the remaining bits. For example, in the CY2037, between the 0000000-0000001 tuning states, the least significant bit has a sensitivity of about 8 ppm; between the 1111110-1111111 states, the least significant bit has a sensitivity of about 2 ppm. Limiting the tuning parameter range will, however, make finding an acceptable set of parameters more difficult.
Thus, with the high level of precision afforded by, for example, the CY 2037, it is possible to avoid the xe2x80x9cfinal platexe2x80x9d operation of fabricating an oscillator, using a raw crystal having an error of, for example, up to 2,000 to 3,000 ppm from a nominal desired value. In accordance with the present invention, a program executing on a local host or embedded processor reads a value of the oscillator output and tuning sensitivity, and calculates values of P, Q, and divider select to achieve a desired output frequency range. The tuning algorithm then compensates for residual error, within an error tolerance. For example, such a program is written in Visual Basic(trademark), C, and Access database languages.
This switch capacitor tuning, for potential elimination of the final plate process, takes advantage of the following equation for crystal frequency vs. load capacitance, per equation 2:
F1=Fr*(C1/(2*C0+CL)+1)xe2x80x83xe2x80x83Eq. 2
This method therefore measures the F1, at 8-15 tuning values, for example of a CY2037 device. This implies an approximate value for C1 at each tuning value, and then allowing calculation of Fr, C0, C1 and Cstray. This results in the ability to tune the finished oscillator, even with a relatively inaccurate crystal.
The programming interface provides both read and write functions. For reading, the system allows confirmation of the CY2037 and confirmation of the full programming of the CY2037. For writing, the system allows selection of current row, programming of the selected row, and loading of the shadow register with a specified bit pattern.
Where the output is intended to be human readable, the read bit pattern may be annotated, and therefore decoded into portions. In addition, the programming device may act as a translator for multiple oscillator types, and therefore have different personalities. In that It case, the annotation feature is, for example, part of a normalization feature for data input and output. Typically, however, the required interface is specific for a certain type of oscillator device, and it is more efficient to provide separate personality modules than a multifunctional programming device.
The programmer preferably interfaces with a standard serial port, e.g., an RS-232 port at 9600 Baud, no parity, 8 data bit and 1 stop bit. Of course, other interfaces could be used. including parallel (Centronics), USB, IEEE-488, Firewire (IEEE-1394), I2C bus, or the like. Further, the programmer may employ an HTML interface and act as an embedded web server, for example including a 10 Base T interface with TCP/IP communications protocol.
Typically, the host system will determine the programming parameters, e.g., P, Q, divider select and tuning bits, and for example, may be fully automated, using a predetermined program to communicate with both frequency counter and programming board.
Alternately, the human user interface may be used to manually enter data into a terminal program, for communication to the programming device. Thus, a separate application may be used to determine appropriate multiply, divide, scaling (divider select) ratios and tuning for the desired output frequency, based on the measured crystal frequency characteristics. The user then transfers these to the programming device through the terminal program.
In the case of an automated testing system, the programming device may be directly controlled by an application program, without use of a manual terminal program interface. In this case, raw, unparsed data may be communicated between the programming device and host computer. However, if the programming device is designed to handle multiple oscillator designs, then a data parser may be of use to standardize communications and the application software, in spite of differences in the oscillator integrated circuit design.
The interface for the CY2037 is a four wire interface. The device implements the required Clock/Data In line switch (data/clock), Vpp/Pgm line switch (shift register enable/disable) and Vdd selection (shift/operate), as well as the required programming sequence. The fourth line is a ground.
It is therefore an object of the invention to provide a method for programming a digitally tunable oscillator, comprising the steps of receiving a desired output frequency; determining a tuning effect of a set of digital tuning words on a crystal resonant frequency; calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect; and programming in a nonvolatile memory a valid set of calculated parameters.
It is a further object of the invention to provide an apparatus for programming a digitally tunable oscillator, comprising an input for receiving a desired oscillator frequency; an input for receiving an output frequency of the digitally tunable oscillator; a control for selecting a plurality of tuning states of the oscillator; a computer program for calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on received output frequency of the oscillator during the plurality of tuning states; and a programmer for programming a nonvolatile memory of the oscillator with a valid set of calculated parameters.
It is a still further object of the invention to provide a computer readable medium, containing a program for performing the steps of receiving a desired output frequency; determining a tuning effect of a set of digital tuning words on a crystal resonant frequency; calculating valid parameters of an algorithm for translating and tuning the crystal resonant frequency to a value within an error tolerance of the desired frequency, based on the determined tuning effect; and outputting at least one set of calculated valid parameters.
According to various embodiments of the invention, a desired maximum error tolerance is input, constraining the set of valid oscillator control parameters.
The oscillator is preferably a phase lock loop frequency synthesizer having a multiply parameter and a divide parameter for the frequency translation. The oscillator also preferably has a capacitive load on the crystal, controllable by a digital tuning word to alter a resonant frequency thereof. According to various embodiments of the invention, substantially all available parameters are evaluated in order to determine the potentially valid parameters which meet all design requirements. Alternately, a subset of the theoretically available parameters may be evaluated, for example, where bits of the oscillator memory are preprogrammed, or where other considerations are mandated.
It is another object of the invention to provide a system and method for programming a programmable oscillator having a nonvolatile memory for persistently storing a control algorithm and a tuning control, wherein the tuning effect is determined before programming of nonvolatile memory with the control algorithm. Therefore, the control algorithm is constrained only by a set of available parameters while determining the tuning control, allowing greater degrees of freedom in calculating the valid parameters.
It is a further object of the invention to provide a separate oscillator programming control and calculating means, and communicating the valid set of parameters between the calculating means and oscillator programming control. Thus, the oscillator programming control need not include a human interface or calculating means, simplifying design and reducing oscillator programming control costs.
It is a still further object of the invention to provide a method and system for programming an accurate oscillator wherein the crystal frequency source is grossly tunes and/or is not subject to a final plate process.
It is another object of the invention to provide a system and method for programming an oscillator having a phase locked loop frequency synthesizer and a crystal tuning parameter, wherein the phase locked loop has a multiply parameter and a divide parameter for frequency synthesis from a crystal frequency, and wherein the valid tuning, multiply and divide parameters are calculated based on an intermediate tuning value, sorted by ascending divide parameter, and then evaluated in sorted order for ability of a tuning effect to null frequency error to within a predefined error tolerance.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims taken in conjunction with the accompanying drawings, in which like numerals refer to like parts.